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| Gateway Design Automation ： ウィキペディア英語版 |
Gateway Design Automation
"Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM (Path-Oriented Decision Making) test generation algorithm.〔Goel's role in PODEM invention briefly described in Alberto Sangiovanni-Vincentelli. (November–December 2003) The Tides of EDA. ''IEEE Design and Test of Computers''. p.62. Viewed 20 September 2006 at (UC Berkeley web site ).〕 Verilog HDL was designed by Phil Moorby,〔Design Automation Conference. (2006). ''Awards'' (pdf).(DAC web site ) p. 2〕 who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989." (added. )〔(Verilog.com ) viewed 20 September 2006.〕
== References ==
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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